----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:01:10 12/02/2009 
-- Design Name: 
-- Module Name:    Register - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Reg_16bit is
    Port ( clock : in  STD_LOGIC;
           ena : in  STD_LOGIC;
           r_in : in  STD_LOGIC_VECTOR (15 downto 0);
           r_out : out  STD_LOGIC_VECTOR (15 downto 0));
end Reg_16bit;


architecture Latch_16 of Reg_16bit is

	signal s_out : STD_LOGIC_VECTOR (15 downto 0);
	
begin
		latching: process (clock)
		begin
			if clock = '1' and ena = '1' then
					r_out <= r_in;
			end if;
		end process latching;
end Latch_16;


library IEEE;
use IEEE.std_logic_1164.all;

package mips_register is
	component Reg_16bit
		Port ( clock : in  STD_LOGIC;
				 ena : in  STD_LOGIC;
             r_in : in  STD_LOGIC_VECTOR (15 downto 0);
				 r_out : out  STD_LOGIC_VECTOR (15 downto 0));
	end component;
end mips_register;